`timescale 1ns / 1ps

module spi_signal_mux(
    output wire     o_spi0_miso               ,
    input wire      i_spi0_mosi               ,
    input wire      i_spi0_sclk               ,
    input wire	     i_spi0_ss1                ,
    input wire	     i_spi0_ss2                ,
    input wire	     i_spi0_ss0                ,
    output wire	     o_spi1_miso               ,
    input wire	     i_spi1_mosi               ,
    input wire      i_spi1_sclk               ,
    input wire	     i_spi1_ss1                ,
    input wire	     i_spi1_ss2                ,
    input wire	     i_spi1_ss0                ,
    // external fpga spi load                  
    output wire     o_fpga_spi0_mosi          ,
    output wire     o_fpga_spi0_sclk          ,
	 //hmc7044                              
    output wire     o_hmc7044_spi0_ss         ,
    input  wire     i_hmc7044_spi0_miso       ,
    output wire     o_hmc7044_spi0_mosi       ,
    output wire     o_hmc7044_spi0_sclk       ,
    //lmx2594_a                  
    output wire     o_lmx2594_a_spi1_ss       ,
    input  wire     i_lmx2594_a_spi1_miso     ,
    output wire     o_lmx2594_a_spi1_mosi     ,
    output wire     o_lmx2594_a_spi1_sclk     ,
    //lmx2594_b                          
    output wire     o_lmx2594_b_spi1_ss       ,
    input  wire     i_lmx2594_b_spi1_miso     ,
    output wire     o_lmx2594_b_spi1_mosi     ,
    output wire     o_lmx2594_b_spi1_sclk     ,
    //lmx2594_c                          
    output wire     o_lmx2594_c_spi1_ss       ,
    input  wire     i_lmx2594_c_spi1_miso     ,
    output wire     o_lmx2594_c_spi1_mosi     ,
    output wire     o_lmx2594_c_spi1_sclk
	
);

// spi0     
assign  o_hmc7044_spi0_ss = i_spi0_ss1;
assign  o_spi0_miso = o_hmc7044_spi0_ss  == 1'b0 &  i_hmc7044_spi0_miso ;

assign	o_hmc7044_spi0_mosi  = i_spi0_mosi;
assign	o_hmc7044_spi0_sclk  = i_spi0_sclk;
assign	o_fpga_spi0_mosi     = i_spi0_mosi;
assign	o_fpga_spi0_sclk     = i_spi0_sclk;

// spi1          
assign o_lmx2594_a_spi1_ss  = i_spi1_ss0;             
assign o_lmx2594_b_spi1_ss  = i_spi1_ss1;             
assign o_lmx2594_c_spi1_ss  = i_spi1_ss2;             
assign o_spi1_miso =  o_lmx2594_a_spi1_ss == 1'b0 & i_lmx2594_a_spi1_miso |
                      o_lmx2594_b_spi1_ss == 1'b0 & i_lmx2594_b_spi1_miso |
                      o_lmx2594_c_spi1_ss == 1'b0 & i_lmx2594_c_spi1_miso ;
				   
assign o_lmx2594_a_spi1_mosi  = i_spi1_mosi;
assign o_lmx2594_a_spi1_sclk  = i_spi1_sclk;
assign o_lmx2594_b_spi1_mosi  = i_spi1_mosi;
assign o_lmx2594_b_spi1_sclk  = i_spi1_sclk;
assign o_lmx2594_c_spi1_mosi  = i_spi1_mosi;
assign o_lmx2594_c_spi1_sclk  = i_spi1_sclk;

endmodule
